Asynchronous arbiters or arbiters can resolve (e.g., arbitrate) conflicts between two signals that are received essentially simultaneously. Arbiters play an important role in asynchronous dual port random access memories (RAMs). Arbiters generally have two “request” inputs and two “grant” outputs and resolve conflicts between two conflicting simultaneously received or asserted inputs.
A drawback to conventional asynchronous arbiters can be the presence of metastability conditions. A metastability condition can result from two simultaneously asserted inputs that result in both outputs being either high or at an approximately equal intermediate voltage level. A metastability condition can increase a resolution time by an indefinite amount. Consequently, timing cannot be guaranteed for a conventional asynchronous dual-port RAM subject to a metastability condition.
To better understand various aspects of the embodiments, a conventional asynchronous arbiter will now be described. A conventional asynchronous arbiter is set forth in FIG. 6, and designated by the general reference character 600.
A conventional asynchronous arbiter 600 can receive enable signals CE(L), CE(R), as well as input signals A and B. In response, conventional asynchronous arbiter 600 can provide output signals C (WRITE INHIBIT (L)) and D (WRITE INHIBIT (R)), as well as busy signals /BUSY(L) and /BUSY(R). Ideally, conventional asynchronous arbiter 600 ensures that regardless of whether one or both of signals A and B are active (high in this case), only one of signals C or D is active (low in this case).
The conventional asynchronous arbiter of FIG. 6 includes a latch 602 formed by cross-coupled NAND gates 604 and 606. In addition, NAND gate 608 can receive enable signal CE(L) and output signal C (by way of inverting input) as inputs, and generate signal /BUSY(L). Similarly, NAND gate 610 can receive enable signal CE(R) and signal D (by way of inverting input) as inputs, and generate signal /BUSY(R).
When both input signals A and B are de-asserted (in this case, low) output signals C and D can attain a logical “True” state (in this case, high). When input signal A is asserted (goes high), corresponding output signal C can transition to a logical “low” state. This translates to input signal A “winning” the arbitration. That is, while input signal A remains asserted, other output signal D will remains in the “high” or unselected state, regardless of the value of input signal B. Similarly, if input signal B is asserted alone, output signal D can go to a “low” or selected state, and output signal C can remain in the unselected state regardless of the value of signal A.
However, if both input signals A and B are asserted essentially simultaneously, output signals C and D can be placed in metastable or unresolved state, until latch 602 can settle down in favor of either output signal C or D. The resolution time required for a latch 602 to resolve a metastable state is finite, but can be unpredictable.
The above unpredictability in resolution time can create functional failures in a circuit surrounding the arbiter that can depend on the arbiter making an exclusive choice between outputs C and D in a set period of time. Many conventional approaches to alleviate this problem are known.
One conventional approach that attempts to address the above problem is shown in FIG. 7, and designated by the general reference character 700. Conventional arbiter 700 can include a latch 702, filter gates (704-0 and 704-1), and decision logic 706. In addition, inverters 1702, 1704 and 1706 are included to provide desired logic levels.
Latch 702 can include cross-coupled three-input NAND gates 162 and 163. Gate 162 can receive an enable signal “en_ex”, input signal A, and the output of gate 163 (n<0>), as inputs. Gate 163 can receive input signal B, output of gate 162 (n<1>), and output of decision logic 706 (fb), as inputs.
Filter gates (704-0 and 704-1) can be two-input NAND. NAND gate 13 can receive signal n<1> and an enable signal “a_ex” as inputs, and provide filtered output signal n<2> as an output. Similarly, NAND gate 14 can receive signal n<0> and an enable signal “b_ex” as inputs, and provide filtered output signal n<3> as an output. NAND gates 13 and 14 can be designed as metastability filters. According to well understood techniques, such as transistor sizing and/or transistor threshold adjustment, NAND gates 13 and 14 can provide high output signals when the corresponding input signal n<0> and n<1>, are in a metastable state (assuming the corresponding enable signal “a_ex” or “b_ex” is high).
Decision logic 706 can include an AND-NOR combination circuit 708. An AND portion can receive filtered output signals n<2> and n<3> as inputs along with a power enable signal “en_pwr”. NOR portion can receive as inputs the output of AND portion, as well as enable signal “en_ex” by way of inverter I702. The output of AND-NOR circuit 708 can be feedback signal “fb”.
Referring still to FIG. 7, in the event a metastable condition arises (e.g., both output signals n<0> and n<1> are low, or at some intermediate voltage level), filter gates (704-0 and 704-1) can force filtered output signals n<2> and n<3> to a high level.
Assuming signals “en_pwr” and “en_ex” are both high, in response to filtered output signals n<2> and n<3> being high, decision logic 706 can drive feedback signal “fb” low. This can force output signal n<0> high and hence output signal n<1> low, thus resolving the metastable state and settling the state of latch 702.
In this way, the conventional approach of FIG. 7 makes use of a feedback mechanism to steer an arbiter latch to one side (or output) when the latch gets stuck in metastable condition, thereby yielding a predictable output state.
While the approach of FIG. 7 can be an improvement over that of FIG. 6, such an approach may not be wholly satisfactory for a number of reasons. In particular, the conventional circuit of FIG. 7 can suffer from two disadvantages.
First, the functionality of the circuit can be dependent on the assumption that when latch 702 is in a metastable state, input filtered gates 13 and 14 are always interpreted as logic “low”. That is, the conventional arbiter 700 should ensure that under all circumstances, i.e., under all temperature and voltage conditions, the trip point of NAND gates 13 and 14 are well above the possible metastable levels of signals n<0> and n<1> output from latch 702. Unfortunately, this can be difficult to achieve.
Because latch 702 and filter gates 13 and 14 are two different types of circuits (three-input NAND gates vs. two-input NAND gates), it is probable that in at least some situations their relative trip points will not track one another. Because of this weakness (not isolating the metastable states in a reliable fashion), metastability can propagate to the downstream nodes, potentially causing functional failures.
A second disadvantage can be that the conventional arbiter circuit of FIG. 7 can be prone to kicking-in in undesirable circumstances. For example, even when the two inputs are transitioning into and out of valid states, a feedback effect (signal “fb” going low) may kick-in, causing undesirable glitches.
Such an arrangement is illustrated in FIG. 8. FIG. 8 is a timing diagram showing various signals of FIG. 7, including input signals A and B, feedback signal “fb”, and output signals n<0> and n<1>.
FIG. 8 illustrates how if both latch input signals (A and B) are near simultaneously asserted from a de-asserted state (transition from high to low), latch 702 can decide to assert output signal n<1> low. That is, latch 702 may start to establish input signal A is the “winning” signal. However, before latch 702 completes the transition in output signal n<1>, feedback generated by filter section 704 and decision logic 706 can drive feedback signal “fb” low, which favors driving output signal n<0> low. As a result, output signal n<1> can experience a glitch 800 that can cause functionality problems in following circuit blocks of a device.
The above problem may be aggravated by advanced manufacturing processes. More particularly, current deep submicron technologies can produce devices that can cause latches to settle very fast. In such circumstances, an uncontrolled feedback circuit can hamper the normal functioning of the latch by settling to logic values opposite to those forced by a feedback circuit, or the like.
Accordingly, there is a need for an arbiter circuit that does not propagate metastability state. At the same time, such an arbiter circuit should provide an essentially glitch free output. It is further desirable that such an arbiter circuit has a bounded resolution time, and reliably generate a predictable output state.